All posts by Hamilton

20m Vertical Dipole

My main antenna is a full wave 40m delta loop which also matches well across 20m. While the match is good the pattern is not ideal for DX. EZNEC predicts numerous nodes and nulls and a high take off angle. I have been looking for a better 20m DX antenna while I wait to get a beam up.

At the Club’s (N1FD) recent VE session a Radio Wavz 20m Dipole was described as having good DX performance when mounted as a vertical.  At $39 including a 1:1 choke balun, I decided to try it.

I shot a rope over a branch at 65′, attached and sealed the coax, and hauled the dipole up. The coax needs to come away from the vertical at roughly 45° to minimize the coupling to the lower antenna wire.

Vertical Dipole - The Balun is hung at a right angle
Figure 1 The Balun is hung at a right angle

A paracord is attached to Balun in the opposite direction from the coax to oppose the pull of the coax and is needed to keep the antenna wire vertical as shown in Figure 1.

I used a water bottle to weigh down the lower wire which allows the antenna to move with the tree to avoid damage during high winds.  Figure-2 shows the Delta Loop and to its right the Vertical Dipole. It is difficult to see the Vertical, the green water bottle can be seen just below the center of the figure.

Delta Loop and Vertical Dipole (right)
Figure-2 Delta Loop and Vertical Dipole (right)

After the initial installation, the first step was to measure the VSWR. This can be done using the radio’s VSWR meter or an antenna analyzer. If the antenna had to be brought down to adjust its length I wanted to do it before I secured the cables and finished the installation.

The antenna analyzer measured a <1.8:1 VSWR from 13.4 MHz to 14.35 MHz. A good match over 1 MHz of bandwidth is very good. The resonate point with a 1.2:1 VSWR was at 13.9 MHz. The antenna was long which is normal “out of the package” without any tuning. With a little shortening, the match was <1.5:1 across the entire 20m band and less than 1.2:1 at band center. This is better than EZNEC predicted. The VSWR measurement includes 100′ of LMR-400 which will improve the apparent match a little. I suspect most of the improvement is from the interaction with the angled coax. It is also possible the balun isn’t a perfect 1:1 as described by Radio Wavz. The antenna has a very good match across the full band and does not need a tuner.

The vertical dipole’s noise floor was S3 (-106 dBm 3 kHz BW) which is good. I had assumed it would be much higher because it was a vertical. It is only an S unit higher than the Delta loop which measured S2 (-111 dBm 3 kHz BW).

EZNEC shows a low 10-45 degree take off angle and no NVIS capability with the top of the vertical dipole at 65′ as seen in Figure 3.

Vertical Dipole EZNEC Analysis at 65' height over poor ground
Figure 3 EZNEC Analysis at 65′ height over poor ground

Based on EZNEC it should be better for DX than for local communications.  In practice, this is the case.

For the first test, I tuned into the afternoon 20m Net. Most of the stations are within 400 miles of my QTH. The Delta Loop had a 10 dB to 20 dB SNR (signal to noise ratio) advantage at this range. An Agilent spectrum analyzer was used for these measurements.  Tuning the band I found Vancouver BC, WA, OR, CA, and Ireland. Only Ireland could be heard with the Loop. I have never heard any 20m stations in the Pacific NW  while using the loop.

The next test was to use the RBN (Reverse Beacon Network) to measure the antennas DX performance. For those unfamiliar with RBN, there are roughly 140 stations worldwide that are connected to CW Skimmers. Using CW you send a series of CQs and your call sign. If you are detected you are added to a Spot Collector which is accessible on a website or via telnet.

I transmitted on 14,037.5 when using the Loop and 14,038.5 when using the Vertical Dipole.  By using two frequencies I could tell which antenna the Spot was reporting. Also, most of the RBN stations will not respond to a second call too soon after reporting the first intercept. With a quick QSY, I could transmit on the opposite antenna without waiting. Figure 3 is a sample of the RBN Spots.

RBN Spots
Figure 3 RBN Spots

I plotted the distance to the Spots versus the reported SNR. This can be seen in Figure-4. The number of RBN nodes is limited and some of the nodes listed on the RBN website might not be available, especially during this weekends SSB contest.   Also, the band conditions will impact the range and number of stations reached.

Delta Loop vs. Vertical Dipole - SNR versus Range
Figure-4 SNR versus Range

Note that where two data points (Red and Blue) are at the same range and therefore directly above each other both antennas were spotted by the same station.   If the Spot could hear the Loop it always heard the Vertical Dipole but there were many times the Spot heard the Vertical Dipole and not the Loop.

KM3T is only 3.1 miles from my QTH. As seen in the RBN screen capture and on the plot the SNR with the Vertical is 55 dB and only 45 dB with the loop. The plot also shows an SNR=9 dB data point for the Vertical near the Y axis and no matching Blue data point for the Loop. This station was 70 miles away in MA. Both of these data points rely on ground waves and the Vertical Dipole has an advantage when compared with the Loop.

Overall beyond 1000 miles the Vertical Dipole clearly performs better than the Delta Loop and will definitely add DX to a log.

In summary when mounted high the vertical dipole retains the low take off angle of a 1/4 wave ground mounted vertical. It does not need ground radials and ground losses are reduced. It can be placed above obstructions such as a barn or house. It only needs one high support and it does not require a tuner.

It isn’t a hex beam or a yagi due to the impact of ground losses on the gain, but at $40, no tower required, it is a great antenna. It is very stealthy as well.

Hamilton, K1HMS

Parts Store On A Chip (CPLD / FPGA) – CPLD’s in the Shack

My “go to” tool when breadboarding is often an evaluation board with a Xilinx CPLD. A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both.

A CPLD is like a Digikey catalog on a chip. It includes simple logic devices like ANDs, NANDs, ORs, NORs, and XORs. There are Flip-Flops, FIFOs, MUXs, Counters, Compares, Latches, pull ups, pull downs, tri-state I/O, Schmitt triggers, and the list goes on and on. A small device has 64 user I/O ports and larger devices can have 100s of ports.

CPLD - A wide range of devices is available.
Figure-1 A wide range of devices is available.

Figure-1 is the pallet of available parts. The Category Logic is selected; the first 13 device showing are ANDs ranging from 2 to 5 inputs. An “and1b1″ is a simple AND with one standard input and 1 inverting input. There are also designs for RS-232/422, SPI, I2C etc on the web that are constructed from the pallet devices.

Once a symbol is placed on the schematic you can right click on the device and see its description and logic table. Most of the time the VHDL code is also available for editing if desired. Knowledge of VHDL or Verilog is not required to design at the schematic level. The schematic symbols are connected by placing a wire or bus between ports.

Ports can be configured into various I/O Standards. A “bank” can be configured for 5.0-volt logic and another bank can be 3.3V, 1.8V or 1.2V which is useful if you need “Glue Logic” between one standard and another.

The best part is it is very easy to take advantage of this capability. There are numerous eval-boards priced from $3-$15 for a board like the one in Figure 2.

$10 CPLD evaluation board
Figure-2 $10 CPLD evaluation board

At the $50 mark, you can get a board with LED lights/digits, buttons, switches, pots, etc.

At higher price points you can get USB, GB Ethernet, HD-LCDs and HMDI ports but they may be beyond schematic level designs and will require VHDL or Verilog skills.

In contrast, there is the dead bug (Figure 2a) approach. The disadvantage to this approach is you must have the “bugs” on hand, the clock rate is limited to a few MHz due to wire length (CPLD clock speed can be > 125MHz), and “edits” are done with a soldering iron with the power off instead of a text editor with the circuit running.

Two dead bugs
Figure-2a Two dead bugs

The software tool to configure the CPLD is the Xilinx ISE WebPack which is a free download and a programming dongle that can range from $15 and up. Many boards include the programmer on the board eliminating the need for a dongle, all that is needed is a USB cable to the PC.

I have designed a small device in Figure-3 as an example. There are 3 distinct circuits. I have included an inverter for those times you have a signal that needs to be inverted, an 8 bit counter with a parallel output, and a Flip-Flop that shares the input with the inverter circuit.

Design ready to download onto a CPLD
Figure-3 Design ready to download onto a CPLD

The example shows an Inverter/Flip-Flop circuit and a counter circuit. They are independent of each other. The ability to have a large number of independent parallel circuits gives CPLD/FPGA an advantage over microprocessors in certain applications, especially DSP circuits.

The Xilinx ISE tool will produce a block diagram (Figure-4) of the circuit.

CPLD Top Level Block Diagram
Figure-4 Top Level Block Diagram

By clicking on the block diagram you can open the detailed circuit (Figure-5), further, the complex elements within the circuit can be expanded.

 

Detail Schematic produced from synthesized CPLD design
Figure-5 Detail Schematic produced from synthesized CPLD design

These are not a “redraw” of the original schematic. They represent the final design after the schematic was translated into HDL by ISE and a circuit design synthesized from the HDL code. This process is transparent to the user.  This capability is very useful when designing in HDL. It allows you to discover errors in the code quickly.  It is easier for many hardware designers to “debug” the firmware code by following wires on a schematic.

A CPLD board can be very useful in the Ham Shack when positive control is needed. In situations with multiple antenna switches, band switches, and amplifier keyer lines where control logic is important a CPLD design is a great approach. Once the required logic and lockouts are determined the logic design can be completed at the schematic level and the CPLD configured.

The CPLD uses Combinational Logic, it is completely deterministic. Even with a lot of care, a microprocessor has the potential to fall into a disallowed state that could potentially damage equipment. By using hardwired logic this becomes nearly impossible without an actual hardware failure.

If you find an error or change your station simply change the schematic and re-flash the CPLD. (The days of one-use fused link logic are behind us).

Xilinx ISE includes the capability to write a test bench where you describe the full range of inputs and it will display the corresponding output states and timing in Logic Analyzer style. The displayed data is based on actual physical device timing constraints and will allow you to trap switching glitches and logic errors.

While I have focused on CPLDs everything written above can be applied to FPGAs. The different is 100% transparent except the cost may be slightly higher for a small FPGA evaluation board. The first step up from a CPLD in the Xilinx line would be a Spartan device which has considerably most resources and higher performance. While schematic input is an easy place to start ISE is a widely used tool for both VHDL and Verilog HDL coding. It is hoped you would at least dabble in HDL once you have a board.

I have described getting started with CPLDs as easy. I find it much easier than coding in C where just keeping the tool set happy with its countless libraries that must be on the correct path and 100 other ways to generate errors.  I enjoy coding in VHDL, for me, it is easier to “think” in terms of wires and buses. With that said there are a few minor hills to get over to start using ISE to configure a CPLD/FPGA.

Here are the three largest issues:

  1. ISE WebPack is four 2 GB files. An 8 GB total download of compressed .tar files.
  2. The process of generating and downloading the free license can be a challenge, and then you get to install it.
  3. Getting an inexpensive aftermarket programming dongle to be recognized by ISE and the PC can require patience.

Once the program is installed and working the rest of the issues are nits. As a hardware designer, I consider them nits.

  1. You can only attach one wire to a port pin if you want more than one it must be to a buffered pin.
  2. The logic must be deterministic, in short, you cannot have two outputs tied together unless it is through a AND, OR or similar. Each connection must have a clear “true or false” state.
  3. The ports you defined in the schematic must be routed to a pin on the CPLD. This is accomplished with a .ucf or User Constraint File. The constraint file format looks like this: NET “name” LOC = “P(pin number)”;  That is it.

The following is part of the Constraint file for the schematic shown in Figure 3 and is compatible with the eval-board shown in Figure-2.

# This is an example of a constraint file
NET "Flip_Flop_Output"LOC = "P5";
NET "Clock"LOC = "P30";
NET "Inverter_In"LOC = "P7";
#NET "P7"LOC = "P1";
'#' indicates the line is commented out and is ignored

Most boards are supplied with a constraint file so you know which pins go to the switches and LEDs, and which ones you can use. If their names are P1, P2, P3 in the constraint file and you have named your ports Clock, Clear, and Count you will hang up on an error. The same is true if you do not use ports P7-P64 in the design and leave them un-commented in the constraint file. If it is in the design it must be in the constraint file, and vice-versa.

  • There is a short list of special Key words to include CLK, CLR, and NET. These and other Key words must be avoided until you get past the basics and understand their use.

ISE does a good job of providing a Web link for errors in ISE. The linked page will tell you the problem, likely cause, and the solution.

Here is a schematic of a 4 digit display, it still has 44 user pins available.

CPLD used to drive a 4 Digit Display
Figure-6 CPLD used to drive a 4 Digit Display

 

 

 

 

 

 

 

 

If nothing else ISE is a great way to draw schematics.

If you are interested in adding CPLDs and FPGAs to your tool kit I would be more than glad to get you set up and give you a short tutorial.

Hamilton,  K1HMS

CW Ops Using Winkeyer and a Decoder

Ira (KC1EMJ) and I helped set up the IC-7300 80, 15, and 10m CW station. We were short a CW operator.  Having my license for only 8 months with over 1000 SSB QSOs and zero CW contacts in the log I wasn’t a CW op but the station was available and the field day clock was running. My ability to copy is improving but very limited. On the run up to Field Day I had some experience with N1MM, Fred (AB1OC) added a WinKeyer and loaded his macros, and I had CW Skimmer already installed on the laptop. What more could I need?

It only took a few minutes to get the ICOM IC-7300 and CW Skimmer setup for reliable decoding. It was exciting when the decoder finally started displaying “CQ CQ FD DE CALL-SIGN” for each station I tuned in. I have included a simulated display showing a decoded message.image001 I was in business! Or so I thought.

With Search and Pounce selected, the WinKeyer was setup so the laptop keyboard’s F1 key was QRL?, F2 the exchange (class and section), F3 TU for “thank you” and so on through F9.  I assumed one would start with F1, and progress to F2, and then F3, what is QRL anyway? After decoding a “CQ FD call-sign” and entering the call into N1MM I hit F1, and then decoded a “don’t say you do not hear me”.

I moved up the band and tried it again with the same result. It was great I was making contacts, but not so great they was throwing bricks. A quick check with Mike (K1WVO) I found QRL is “Are you busy?”. As a Phone op I had never used QRL, we just ask “is the frequency is in use”. Soon I was responding with N1FD instead of QRL? The Caller returned his class and section.

With his call entered into N1MM it was easy to send his call sign with a tap of the F5 key, F2 for 7A and NH, and after his TU I would send a TU and QSY to the next station and repeat the process. It had transitioned from real exciting (meaning a bit stressful)  to real fun fairly quickly.  The lesson I learned is to take the time to understand the message stored behind each “F” key even when time is short and the contest or Field Day has started.

The experienced CW operators were using the same process that I was using with WinKeyer, N1MM, and the keyboard. The one difference  is they were decoding CW with their ears, and not a decoder.

It wasn’t long before I ran out of new stations to work. I switched from searching for stations in “Search and Pounce” mode  to “Run” meaning I stayed on one frequency and called CQ. The F1 key became CQ. It wasn’t long before I had a short run of 5-6 QSOs one right after another, but it quickly came to an end. There are few targets on 80m in the early evening and I worked them all. I was headed home just as the band was heating up at midnight… Next year I’ll take the midnight to daylight shift and plan to copy code with my ears…and not a decoder.

With a little practice, this form of operating is effective for contests and Field Day where the exchange is simple. The high rate you can add new stations to the log definitely makes it fun.

Hamilton (K1HMS)

Silent Keys

When my father passed on years ago to our surprise uniformed US Navy officers appeared at the funeral and passed a flag to my mother for his service during WWII. Years ago something similar occurred at my wife’s father’s service except it was USAF, he was a B-17 radioman and survived his 35 mission over Germany, over 1/3 of all crews didn’t.

Many SKs leave their spouses with wires, towers, and equipment, some worth considerable money. I haven’t formulated a plan and some of the issues and liabilities are daunting but wouldn’t it be nice if a clubs “SK Committee” contacted the widow and offered to come by to review the equipment and provide reliable contact names for its sale or removal.

Maybe the initial contact is simply a condolence card from the club or possibly a certificate of thanks from the club. Accompanying it might be a list of resources (creditable tower installers, HRO consignment, etc.) and a contact number if they have questions dealing with a shack.

I’m absolutely not suggesting we take down towers or appraise equipment or any other idea that will get someone hurt or the club in legal trouble. I am suggesting we take the opportunity to recognize the SKs contribution to Amateur Radio to their spouse and provide a bit of guidance on decommissioning the shack while avoiding those that would give them 10 cents on the dollar while dropping a beam through their roof.

Just a thought…

Hamilton, K1HMS